The behavioral model of a split capacitor array involved in the successive approximation register ADC and taking into account the effect of parasitic capacitors. Russian Microelectronics Volume 42, Issue 4, July 2013, Pages 253-259

14 сентября 2018
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Вид публикации Статья
Контактные данные автора публикации Osipov, D.L. , Bocharov, Yu.I., Butuzov, V.A.
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Аннотация

The analysis of the effect of the parasitic capacitors on the split capacitor array digital-to analog converter for use in the successive approximation register analog-to-digital converter is presented. The Verilog-A model of the split capacitor array is developed based on the analysis. The advantages of using this model in the context of the top-down design methodology are considered.
Indexed keywords
Analog converters; Behavioral model; Parasitic capacitors; Split-capacitor arrays; Successive approximation register adc; Successive approximation register analog-to-digital converter; Top-down designs; Verilog-a models
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