Design of 65 nm CMOS SRAM for space applications: A comparative study . Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS 28 October 2014, Article number 6937379

14 сентября 2018
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Вид публикации Тематический материал
Контактные данные автора публикации Gorbunov, M.S.ab , Dolotov, P.S.a , Antonov, A.A.a , Zebrev, G.I.b, Emeliyanov, V.V.c, Boruzdina, A.B.d, Petrov, A.G.d, Ulanova, A.V.d a Scientific Research Institute of System Analysis, Russian Academy of Sciences, Nakhimo
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Аннотация

We study the design of different SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the localization of a strike. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination. © 2013 IEEE.



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Author keywords

CMOS; critical charge; DICE; guard rings; heavy ions; MCU; protons; RHBD; SBU; SEU; SRAM; TID
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